1. Field of the Art
The invention relates to digital circuits for supplying, from a master clock signal, at a frequency or pulse rate f, at least one rectangular signal at a lower frequency (M/N)f, M being an integer and N another integer greater than M and even. It has numerous applications. For instance, it may be used for processing a clock signal at frequency f recovered from a TV signal in accordance with the C-MAC or D2-MAC-Packet standard by filtering the signal and for generating the signal at frequency (2/3)f required for expanding the compressed data and speech signals in the receiver. It is also suitable for generating, from a master clock at frequency f, successive row and column decoding signals at frequency (M/N)f, offset with respect to each other and without overlap, for example for reading from or writing into a matricial memory.
2. Prior Art
Numerous frequency divider circuits are already known. Most of them use a phase locked loop or PLL. FIG. 1 shows, by way of example, a circuit which supplies frequency 2f/3 and which may be used for generating the 13.5 MHz clock from the 20.25 MHz master clock recovered by a television receiver from a C-MAC or D2-MAC/Packet signal.
The recovered signal at frequency f is applied to a divide-by-three divider 10 whose output is connected to one of the inputs of a phase comparator 12. The error signal delivered by the comparator 12 is subjected to low pass filtering in a filter 14 which delivers a phase error signal. The error signal is applied to a voltage controlled oscillator (VCO) 16. A divide-by-two divider 18 receives the signal from the oscillator 16 and delivers a voltage signal substantially at frequency 2f/3 to the phase comparator 12. The output voltage, at frequency 2f/3, is taken from the output of the oscillator.
Such a phase locked loop circuit has drawbacks. It includes analog components which are expensive, difficult to integrate in LSI circuits further including digital components, sensitive to noise and to temperature variations. The drawbacks are particularly serious in consumer apparatuses such as television sets. The operating range is limited to a restricted frequency band about a set value. The synchronization time during which there is no useful output signal is substantial, particularly at high frequencies and if the operating frequency band is wide.
Pulse rate multipliers using cascaded flip-flops are also well known in the art. Such a multiplier is disclosed in U.S. Pat. No. 3,230,353 (Greene et al). It is not adaptable to delivery of pulses at a rate lower than the input rate for the intended purpose.